library verilog;
use verilog.vl_types.all;
entity dti_shftreg is
    generic(
        LENGTH          : integer := 5
    );
    port(
        clk             : in     vl_logic;
        load_n          : in     vl_logic;
        shift_n         : in     vl_logic;
        s_in            : in     vl_logic;
        p_in            : in     vl_logic_vector;
        p_out           : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of LENGTH : constant is 1;
end dti_shftreg;
